1. Field of the Invention
This invention relates to integrated circuits and particularly to test structures for electrically detecting back end of the line failures.
2. Description of Background
Current semiconductor integrated circuits (ICs) are mass produced by forming an array of chips electrically connected together on a thin semiconductor wafer. Each array location is known as a die, and each die can include a multilayered IC chip or a structure for test or alignment. A connection pad for connecting to circuit inputs and outputs (I/Os) and a power source(s) can be located at the surface of each die. An insulator can surround the connection pads for insulating them from each other. During far back end of the line (FBEOL) processing, a via can be etched through one or more passivation layers down to the connection pad of each die. Each via can be filled with a metal interconnect to provide connection to the underlying connection pad. Solder balls (e.g., controlled collapsible chip connections (C4s)) can then be formed or bumped on the pads for conducting electrical signals from the integrated circuit to a substrate connected to a printed circuit board (PCB).
During performance testing, test fixtures can contact inputs to the C4 solder balls to ensure electrical continuity between the various connection pads of the die. The test fixtures can be used to electrically detect the failure of the circuit due to damage such as cracks. Such cracks can arise as a result of the module being subjected to thermal cycling that causes the die to expand and contract, usually at a different rate than the substrate (e.g., a Flip Chip Plastic Ball Grid Array (FCPBGA)) to which it is attached. Unfortunately, such testing usually only detects C4 solder-specific failures. However, BEOL failures directly associated with the BEOL insulator region, passivation layers, and interconnect remain undetectable using such testing.
In the past, this inability to detect BEOL failures has been overcome by additionally examining semiconductor die using a scanning electron microscope (SEM), thermal electron microscope (TEM), a focused ion beam (FIB), sonoscan imaging, etc. However, this type of examination can itself cause damage to the die. Further, the examination of the die can only be performed periodically rather than continuously in real time, thus limiting the understanding of the mechanism and root cause of the BEOL failures. Moreover, such techniques cannot detect damage after the chip is fully assembled to the substrate, including damage to the lid and heat sink attachment.
A need therefore remains for a way to electrically detect BEOL damage not directly affecting the main connections to the conductive pads disposed near the high risk areas of the die.